library ieee;
use ieee.std_logic_1164.all;
use work.ALU_components_pack.all;
entity binary2BCD is
 
  generic (
	WIDTH : integer := 8           	-- 8 bit binary to BCD converter
	);
  port (
	binary_in : in  std_logic_vector(WIDTH-1 downto 0);  -- binary input width
	BCD_out   : out std_logic_vector(11 downto 0)  -- BCD output, 12 bits [4|4|4] to display a 3 digit BCD value when input has width 8
  );
 
end binary2BCD;
architecture structural of binary2BCD is
--type bcd is std_logic_vector();
 signal bcd : std_logic_vector(11 downto 0);
 signal bin : std_logic_vector(7 downto 0);
 
 
begin 


 BCD_out <= bcd;
end structural;